Flash memory is generally well-known as an example of a nonvolatile semiconductor memory. One example of a semiconductor storage device comprising flash memory is the SSD (Solid State Drive). An SSD is advantageous compared to a HDD (Hard Disk Drive) in that it features higher read and write processing performance.
A flash memory comprises multiple cells, and a single cell, for example, maintains two states over time. More specifically, digital data is recorded by associating one of the two states of the cell with the bit value “1”, and the other of the two states with the bit value “0”. For example, in the case of a SLC (Single Level Cell) type flash memory, which is an example of a semiconductor recording element, digital data is recorded by associating a state in which an electron is injected onto a FG (Floating Gate) of the cell with the bit value “0” and associating a state in which an electron is not injected onto the cell FG with the bit value “1”, and maintaining this state over time.
The downscaling of flash memory circuits has made progress in recent years, and as this downscaling has progressed, recorded data storage capabilities of a flash memory have dwindled. The reason for this is that the difference between an injected electron state and a non-injected electron state is narrowed by downscaling, and when a flash memory is being read, this increases the probability of a cell, which would have been originally determined to be injected with an electron, being erroneously judged to be a cell, which has not been injected with an electron, and, alternatively, increases the probability of a cell, which would have been originally determined not to be injected with an electron, being erroneously judged to be a cell, which has been injected with an electron. For this reason, fail bits (a bit associated with a cell for which the state was erroneously determined to be different), which are included in read data from a flash memory, have increased in recent years, increasing the likelihood of the correction capabilities of the correction codes assigned to data being overwhelmed and data being lost. The increase in the number of fail bits is more conspicuously apparent as a result of the progress of cell deterioration in accordance with cell rewriting. For this reason, the number of erases possible in a flash memory is decreasing in accordance with advances in downscaling.
Data is read from a flash memory using one or more prescribed types of parameters. A parameter, which is used in a data read, will be called a “read parameter” hereinbelow.
When a read parameter is inappropriate, a large number of fail bits occur in the read data. For example, a flash memory generally corrects a fail bit in read data by using a correction code such as ECC, but when a read parameter is inappropriate, the probability of the read data having a larger number of fail bits than the number of fail bits allowed increases. This makes it impossible to correct the read data.
Consequently, a technology for changing a read parameter and using the post-change read parameter to read data from a flash memory is known. Hereinafter, using an unchanged prescribed read parameter to read data will be referred to as a “normal read”, and changing a read parameter and using the post-change read parameter to read data will be referred to as a “special read”.
Technology for performing a special read includes the technology disclosed in Patent Literature 1. Patent Literature 1 discloses a technology for changing a reference voltage at the time of a read (a read voltage) for determining the presence or absence of an injected electron in a cell, and discloses two examples of a method for changing the reference voltage. One example is a method in which a flash memory controller notifies a flash memory of a change in the read reference voltage value and this changed value, and the flash memory internally changes the read reference voltage. The other example is a method in which, in a case where the configuration is such that the flash memory controller creates a read voltage and supplies this read voltage to the flash memory at the time of a read, the flash memory controller supplies this read voltage by changing the read reference voltage. Patent Literature 1 discloses technology for changing the read reference voltage in various ways in an attempt to reduce the fail bits when the number of fail bits occurring in read data at the time of a read exceeds that which could be corrected by the correction code (ECC: Error Correcting Code) assigned to the data, making it impossible to read the data accurately.